Two-terminal reversibly switchable memory device

ABSTRACT

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 15/797,452, filed on Oct. 30, 2017, which is a continuation of U.S. patent application Ser. No. 14/844,805, filed on Sep. 3, 2015, now U.S. Pat. No. 9,831,425, which is a continuation of U.S. patent application Ser. No. 14/463,518, filed Aug. 19, 2014, now U.S. Pat. No. 9,159,913, which is a continuation of U.S. patent application Ser. No. 12/456,627, filed Jun. 18, 2009, now abandoned, which is a continuation of U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 10/934,951, filed Sep. 3, 2004, now U.S. Pat. No. 7,538,338, and which is a continuation-in-part of U.S. patent application Ser. No. 10/773,549, filed Feb. 6, 2004, now as U.S. Pat. No. 7,082,052, all of which are hereby incorporated by reference in their entirety for all purposes.

BACKGROUND OF THE INVENTION Field of the Intention

The present invention relates to computer memory and more specifically to non-volatile memory.

Description of the Related Art

Memory can either be classified as volatile or nonvolatile. Volatile memory is memory that loses its contents when the power is turned off. In contrast, non-volatile memory does not require a continuous power supply to retain information. Most non-volatile memories use solid-state memory devices as memory elements.

Since the 1960s, a large body of literature has evolved that describes switching and memory effects in metal-insulator-metal structures with thin insulators. One of the seminal works was “New Conduction and Reversible Memory Phenomena in Thin Insulating Films” by J. G. Simmons and R. R. Verderber in 301 Proc. Roy. Soc. 77-102 (1967), incorporated herein by reference for all purposes. Although the mechanisms described by Simmons and Vederber have since been cast into doubt, their contribution to the field is great.

However, nobody has successfully implemented a metal-insulator-metal structure into a commercial solid-state memory device. In the text “Oxides and Oxide Films,” volume 6, edited by A. K. Vijh (Marcel Drekker 1981) 251-325, incorporated herein by reference for all purposes, chapter 4, written by David P. Oxley, is entirely devoted to “Memory Effects in Oxide Films.” In that text, Oxley says “It is perhaps saddening to have to record that, even after 10 years of effort, the number of applications for these oxide switches is so limited.” He goes on to describe a “need for caution before any application is envisaged. This caution can only be exercised when the physics of the switching action is understood; this, in turn, must await a full knowledge of the transport mechanisms operating in any switch for which a commercial use is envisaged.”

In 2002, over twenty years after writing that chapter, Oxley revisited the subject in “The Electroformed metal-insulator-metal structure: A comprehensive model” by R. E. Thurstans and D. P. Oxley 35 J. Phys. D. Appl. Phys. 802-809, incorporated herein by reference for all purposes. In that article, the authors describe a model that identifies the conduction process as “trap-controlled and thermally activated tunneling between metal islands produced in the forming process.” “Forming” (or “electroforming”) is described as “the localized filamentary movement of metallic anode material through the dielectric, induced by the electric field. Here it is important to note that the evaporated dielectric may contain voids and departures from stoichiometry. When resulting filaments through the dielectric carry sufficient current, they rupture to leave a metal island structure embedded in the dielectric. Electronic conduction is possible through this structure by activating tunneling.”

However, the authors caution, “The forming process is complex and inherently variable. Also tunneling barriers are susceptible to changes in their characteristics when exposed to water vapour, organic species and oxygen . . . . Thus, device characteristics can never be expected to be produced consistently or be stable over long periods without passivation, effective encapsulation and a better understanding of the dynamics of the forming process.”

In seemingly unrelated research, certain conductive metal oxides (CMOs), have been identified as exhibiting a memory effect after being exposed to an electronic pulse. U.S. Pat. No. 6,204,139, issued Mar. 20, 2001 to Liu et al., incorporated herein by reference for all purposes, describes some perovskite materials that exhibit memory characteristics. The perovskite materials are also described by the same researchers in “Electric-pulse-induced reversible resistance change effect in magnetoresistive films,” Applied Physics Letters, Vol. 76, No. 19, 8 May 2000, and “A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films,” in materials for the 2001 Non-Volatile Memory Technology Symposium, all of which are hereby incorporated by reference for all purposes.

In U.S. Pat. No. 6,531,371 entitled “Electrically programmable resistance cross point memory” by Hsu et al, incorporated herein by reference for all purposes, resistive cross point memory devices are disclosed along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes.

Similarly, the IBM Zurich Research Center has also published three technical papers that discuss the use of metal oxide material for memory applications: “Reproducible switching effect in thin oxide films for memory applications,” Applied Physics Letters, Vol. 77, No. 1, 3 Jul. 2000, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTi03 single crystals,” Applied Physics Letters, Vol. 78, No. 23, 4 Jun. 2001, and “Electric current distribution across a metal-insulator-metal structure during bistable switching, “Journal of Applied Physics, Vol. 90, No. 6, 15 Sep. 2001, all of which are hereby incorporated by reference for all purposes.

There are continuing efforts to incorporate solid state memory devices into a commercial non-volatile RAM.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1A depicts a perspective view of an exemplary cross point memory array employing a single layer of memory;

FIG. 1B depicts a perspective view of an exemplary stacked cross point memory array employing four layers of memory;

FIG. 2A depicts a plan view of selection of a memory cell in the cross point array depicted in FIG. 1A;

FIG. 2B depicts a perspective view of the boundaries of the selected memory cell depicted in FIG. 2A;

FIG. 3 depicts a generalized cross-sectional representation of a memory cell that can be used in a transistor memory array;

FIG. 4A depicts a block diagram of a representative implementation of an exemplary 1 MB memory;

FIG. 4B depicts a block diagram of an exemplary memory that includes sensing circuits that are capable of reading multiple bits;

FIG. 5A depicts a block diagram representing the basic components of one embodiment of a memory element;

FIG. 5B depicts a block diagram of the memory elements of FIG. 5A in a two-terminal memory cell;

FIG. 5C depicts a block diagram of the memory element of FIG. 5A in a three-terminal memory cell;

FIG. 6A depicts a block diagram of the memory cell of FIG. 5B where oxygen movement results in a low conductivity oxide;

FIG. 6B depicts a block diagram of a two-terminal memory cell of FIG. 5B where a low conductivity oxide is self-limiting;

FIG. 7 depicts a block diagram of a two-terminal memory cell using another memory element embodiment;

FIG. 8A depicts a block diagram of the memory cell of FIG. 7 where a low conductivity region is created in a mixed valence oxide; and

FIG. 8B depicts a block diagram of the memory cell of FIG. 8A that includes an oxygen repository.

It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGs. are not necessarily to scale.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the present invention.

The Memory Array

Conventional nonvolatile memory requires three terminal MOSFET-based devices. The layout of such devices is not ideal, usually requiring an area of at least 8f² for each memory cell, where f is the minimum feature size. However, not all memory elements require three terminals. If, for example, a memory element is capable of changing its electrical properties (e.g., resistivity) in response to a voltage pulse, only two terminals are required. With only two terminals, a cross point array layout that allows a single cell to be fabricated to a size of 4f² can be utilized.

FIG. 1A depicts a perspective view of an exemplary cross point memory array 100 employing a single layer of memory. A bottom layer of x-direction conductive array lines 105 is orthogonal to a top layer of y-direction conductive array lines 110. The x-direction conductive array lines 105 act as a first terminal and they direction conductive array lines 110 act as a second terminal to a plurality of memory plugs 115, which are located at the intersections of the conductive array lines 105 and 110. The conductive array lines 105 and 110 are used to both deliver a voltage pulse to the memory plugs 115 and carry current through the memory plugs 115 in order to determine their resistive states.

Conductive array line layers 105 and 110 can generally be constructed of any conductive material, such as aluminum, copper, tungsten or certain ceramics. Depending upon the material, a conductive array line would typically cross between 64 and 8192 perpendicular conductive array lines. Fabrication techniques, feature size and resistivity of material may allow for shorter or longer lines. Although the x-direction and y-direction conductive array lines can be of equal lengths (forming a square cross point array) they can also be of unequal lengths (forming a rectangular cross point array), which may be useful if they are made from different materials with different resistivities.

FIG. 2A illustrates selection of a memory cell 205 in the cross point array 100. The point of intersection between a single x-direction conductive array line 210 and a single y-direction conductive array line 215 uniquely identifies the single memory cell 205. FIG. 2B illustrates the boundaries of the selected memory cell 205. The memory cell is a repeatable unit that can be theoretically extended in one, two or even three dimensions. One method of repeating the memory cells in the z-direction (orthogonal to the x-y plane) is to use both the bottom and top surfaces of conductive array lines 105 and 110, creating a stacked cross point array.

FIG. 1B depicts an exemplary stacked cross point array 150 employing four memory layers 155, 160, 165, and 170. The memory layers are sandwiched between alternating layers of x-direction conductive array lines 175, 180 and 185 and y-direction conductive array lines 190 and 195 such that each memory layer 155, 160, 165, and 170 is associated with only one x-direction conductive array line layer and one y-direction conductive array line layer. Although the top conductive array line layer 185 and bottom conductive array line layer 175 are only used to supply voltage to a single memory layer 155 and 170, the other conductive array line layers 180, 190, and 195 can be used to supply voltage to both a top and a bottom memory layer 155, 160, 165, or 170.

Referring back to FIG. 2B, the repeatable cell that makes up the cross point array 100 can be considered to be a memory plug 255, plus ½ of the space around the memory plug, plus ½ of an x-direction conductive array line 210 and ½ of a y-direction conductive array line 215. Of course, ½ of a conductive array line is merely a theoretical construct, since a conductive array line would generally be fabricated to the same width, regardless of whether one or both surfaces of the conductive array line was used. Accordingly, the very top and very bottom layers of conductive array lines (which use only one surface) would typically be fabricated to the same size as all other layers of conductive array lines.

One benefit of the cross point array is that the active circuitry that drives the cross point array 100 or 150 can be placed beneath the cross point array, therefore reducing the footprint required on a semiconductor substrate. However, the cross point array is not the only type of memory array that can be used with a two-terminal memory element. For example, a two-dimensional transistor memory array can incorporate a two-terminal memory element. While the memory element in such an array would be a two-terminal device, the entire memory cell would be a three-terminal device.

FIG. 3 is a generalized diagrammatic representation of a memory cell 300 that can be used in a transistor memory array. Each memory cell 300 includes a transistor 305 and a memory plug 310. The transistor 305 is used to permit current from the data line 315 to access the memory plug 310 when an appropriate voltage is applied to the select line 320, which is also the transistor's gate. The reference line 325 might span two cells if the adjacent cells are laid out as the mirror images of each other.

Memory Chip Configuration

FIG. 4A is a block diagram of a representative implementation of an exemplary 1 MB memory 400A. Physical layouts might differ, but each memory bit block 405 can be formed on a separate portion of a semiconductor substrate. Input signals into the memory 400A can include an address bus 430, a control bus 440, some power supplies 450 (typically Vcc and ground—the other signals of bus 450 can be internally generated by the 1 MB memory 400A), and a data bus 460. The control bus 440 typically includes signals to select the chip, to signal whether a read or write operation should be performed, and to enable the output buffers when the chip is in read mode. The address bus 430 specifies which location in the memory array is accessed—some addresses going to the X block 470 (typically including a predecoder and an X-decoder) to select one line out of the horizontal array lines. The other addresses go to a Y block 480 (typically including a predecoder and a Y-decoder) to apply the appropriate voltage on specific vertical lines. Each memory bit block 405 operates on one line of the memory chip data bus 460.

The reading of data from a memory array 420 is relatively straightforward: an x-line is energized, and current is sensed by the sensing circuits 410 on the energized y-lines and converted to bits of information.

FIG. 4B is a block diagram of an exemplary memory 400B that includes sensing circuits 415 that are capable of reading multiple bits. The simultaneous reading of multiple bits involves sensing current from multiple y-lines simultaneous.

During a write operation, the data is applied from the data bus 460 to the input buffers and data drivers 490 to the selected vertical lines, or bit lines. Specifically, when binary information is sent to the memory chip 400B, it is typically stored in latch circuits within the circuits 495. Within the circuits 495, each y-line can either have an associated driver circuit or a group of y-lines can share a single driver circuit if the non-selected lines in the group do not cause the unselected memory plugs to experience any change in resistance, typically by holding the non-selected lines to a constant voltage. As an example, there may be 1024 y-lines in a cross point array, and the page register may include 8 latches, in which case they-block would decode 1 out of 128 y-lines and connect the selected lines to block 495. The driver circuit then writes the 1 or 0 to the appropriate memory plug. The writing can be performed in multiple cycles. In a scheme described in PCT Patent Application No. PCT/US04/13836, filed May 3, 2004, incorporated herein by reference, all the 1s can be written during a first cycle and all the 0s can be written during a second cycle. As described below, certain memory plugs can have multiple stable distinct resistive states. With such multi-level resistance memory plugs, driver circuits could program, for example, states of 00, 01, 10 or 11 by varying write voltage magnitude or pulse length.

It is to be noted that such an architecture can be expanded to create a memory where one array handles all the bits of the data bus, as opposed to having multiple arrays, or memory bit blocks as described above. For example, if the data bus, or memory data organization, also called data width, is 16-bit wide, the y-block of one cross point array can be made to decode 16 lines simultaneously. By applying the techniques of simultaneous reads and 2-cycle writes, such a memory chip with only one array can read and program 16-bit words.

Memory Plug

Each memory plug contains layers of materials that may be desirable for fabrication or functionality. For example, a non-ohmic characteristic that exhibit a very high resistance regime for a certain range of voltages (V_(NO−) to V_(NO+)) and a very low resistance regime for voltages above and below that range might be desirable. In a cross point array, a non-ohmic characteristic could prevent leakage during reads and writes if half of both voltages were within the range of voltages V_(NO−) to V_(NO+). If each conductive array line carried ½ Vw, the current path would be the memory plug at the intersection of the two conductive array lines that each carried ½ Vw. The other memory plugs would exhibit such high resistances from the non-ohmic characteristic that current would not flow through the half-selected plugs.

A non-ohmic device might be used to cause the memory plug to exhibit a non-linear resistive characteristic. Exemplary non-ohmic devices include three-film metal-insulator-metal (MIM) structures and back-to-back diodes in series. Separate non-ohmic devices, however, may not be necessary. Certain fabrications of the memory plug can cause a non-ohmic characteristic to be imparted to the memory cell. While a non-ohmic characteristic might be desirable in certain arrays, it may not be required in other arrays.

Electrodes will typically be desirable components of the memory plugs, a pair of electrodes sandwiching the memory element. If the only purpose of the electrodes is as a barrier to prevent metal inter-diffusion, then a thin layer of non-reactive metal, e.g. TiN, TaN, Pt, Au, and certain metal oxides could be used. However, electrodes may provide advantages beyond simply acting as a metal inter-diffusion barrier. Electrodes (formed either with a single layer or multiple layers) can perform various functions, including to: prevent the diffusion of metals, oxygen, hydrogen and water; act as a seed layer in order to form a good lattice match with other layers; act as adhesion layers; reduce stress caused by uneven coefficients of thermal expansion; and provide other benefits. Additionally, the choice of electrode layers can affect the memory effect properties of the memory plug and become part of the memory element.

The “memory element electrodes” are the electrodes (or, in certain circumstances, the portion of the conductive array lines) that the memory elements are sandwiched in-between. As used herein, memory element electrodes are what allow other components to be electrically connected to the memory element. It should be noted that both cross point arrays and transistor memory arrays have exactly two memory element electrodes since the memory plug has exactly two terminals, regardless of how many terminals the memory cell has. Those skilled in the art will appreciate that a floating gate transistor, if used as a memory element, would have exactly three memory element electrodes (source, drain and gate).

Memory Effect

The memory effect is a hysteresis that exhibits a resistive state change upon application of a voltage while allowing non-destructive reads. A nondestructive read means that the read operation has no effect on the resistive state of the memory element. Measuring the resistance of a memory cell is generally accomplished by detecting either current after the memory cell is held to a known voltage, or voltage after a known current flows through the memory cell. Therefore, a memory cell that is placed in a high resistive state R₀ upon application of −Vw and a low resistive state R₁ upon application of +Vw should be unaffected by a read operation performed at −V_(R) or +V_(R). In such materials a write operation is not necessary after a read operation. It should be appreciated that the magnitude of |−V_(R)| does not necessarily equal the magnitude of |+V_(R)|.

Furthermore, it is possible to have a memory cell that can be switched between resistive states with voltages of the same polarity. For example, in the paper “The Electroformed metal-insulator-metal structure: a comprehensive model,” already incorporated by reference, Thurstans and Oxley describe a memory that maintains a low resistive state until a certain V_(P) is reached. After V_(P) is reached the resistive state can be increased with voltages. After programming, the high resistive state is then maintained until a V_(T) is reached. The V_(T) is sensitive to speed at which the program voltage is removed from the memory cell. In such a system, programming R₁ would be accomplished with a voltage pulse of V_(P), programming R₀ would be accomplished with a voltage pulse greater than V_(P), and reads would occur with a voltages below V_(T). Intermediate resistive states (for multi-level memory cells) are also possible.

The R₁ state of the memory plug may have a best value of 10 kΩ to 100Ω. If the R₁ state resistance is much less than 10 kΩ, the current consumption will be increased because the cell current is high, and the parasitic resistances will have a larger effect. If the R₁ state value is much above 100Ω, the RC delays will increase access time. However, workable single state resistive values may also be achieved with resistances from 5 kΩ to 1 MΩ and beyond with appropriate architectural improvements. Typically, a single state memory would have the operational resistances of R₀ and R₁ separated by a factor of 10.

Since memory plugs can be placed into several different resistive states, multi-bit resistive memory cells are possible. Changes in the resistive property of the memory plugs that are greater than a factor of 10 might be desirable in multi-bit resistive memory cells. For example, the memory plug might have a high resistive state of R₀₀, a medium-high resistive state of R₀₁, a medium-low resistive state of R₁₀ and a low resistive state of R₁₁. Since multi-bit memories typically have access times longer than single-bit memories, using a factor greater than a 10 times change in resistance from R₁₁ to R₀₀ is one way to make a multi-bit memory as fast as a single-bit memory. For example, a memory cell that is capable of storing two bits might have the low resistive state be separated from the high resistive state by a factor of 100. A memory cell that is capable of storing three or four bits of information might require the low resistive state be separated from the high resistive state by a factor of 1000.

Creating the Memory Effect with Tunneling

Tunneling is a process whereby electrons pass through a barrier in the presence of an electric filed. Tunneling is exponentially dependent on a barrier's width and the square root of its height. Barrier height is typically defined as the potential difference between the Fermi energy of a first conducting material and the band edge of a second insulating material. The Fermi energy is that energy at which the probability of occupation of an electron state is 50%. Barrier width is the physical thickness of the insulating material.

The barrier height might be modified if carriers or ions are introduced into the second material, creating an additional electric field. A barrier's width can be changed if the barrier physically changes shape, either growing or shrinking. In the presence of a high electric field, both mechanisms could result in a change in conductivity.

Although the following discussion focuses mainly on purposefully modifying the barrier width, those skilled in the art will appreciate that other mechanisms can be present, including but not limited to: barrier height modification, carrier charge trapping space-charge limited currents, thermionic emission limited conduction, and/or electrothermal Poole-Frenkel emission.

FIG. 5A is a block diagram representing the basic components of one embodiment of a memory element 500, FIG. 5B is a block diagram of the memory element 500 in a two-terminal memory cell, and FIG. 5C is a block diagram of the memory element embodiment of FIG. 5A in a three-terminal memory cell.

FIG. 5A shows an electrolytic tunnel barrier 505 and an ion reservoir 510, two basic components of the memory element 500. FIG. 5B shows the memory element 500 between a top memory electrode 515 and a bottom memory electrode 520. The orientation of the memory element (i.e., whether the electrolytic tunnel barrier 505 is near the top memory electrode 515 or the bottom memory electrode 520) may be important for processing considerations, including the necessity of seed layers and how the tunnel barrier reacts with the ion reservoir 510 during deposition. FIG. 5C shows the memory element 500 oriented with the electrolytic tunnel barrier 505 on the bottom in a three-terminal transistor device, having a source memory element electrode 525, gate memory element electrode 530 and a drain memory element electrode 535. In such an orientation, the electrolytic tunnel barrier 505 could also function as a gate oxide.

Referring back to FIG. 5A, the electrolytic tunnel barrier 505 will typically be between 10 and less than 50 angstroms. If the electrolytic tunnel barrier 505 is much greater than 50 angstroms, then the voltage that is required to create the electric field necessary to move electrons through the memory element 500 via tunneling becomes too high for most electronic devices. Depending on the electrolytic tunnel barrier 505 material, a preferred electrolytic tunnel barrier 505 width might be between 15 and 40 angstroms for circuits where rapid access times (on the order of tens of nanoseconds, typically below 100 ns) in small dimension devices (on the order of hundreds of nanometers) are desired.

Fundamentally, the electrolytic tunnel barrier 505 is an electronic insulator and an ionic electrolyte. As used herein, an electrolyte is any medium that provides an ion transport mechanism between positive and negative electrodes. Materials suitable for some embodiments include various metal oxides such as Al₂O₃, Ta₂O₅, HfO₂ and ZrO₂. Some oxides, such as zirconia might be partially or fully stabilized with other oxides, such as CaO, MgO, or Y₂O₃, or doped with materials such as scandium.

The electrolytic tunnel barrier 505 will typically be of very high quality, being as uniform as possible to allow for predictability in the voltage required to obtain a current through the memory element 500. Although atomic layer deposition and plasma oxidation are examples of methods that can be used to create very high quality tunnel barriers, the parameters of a particular system will dictate its fabrication options. Although tunnel barriers can be obtained by allowing a reactive metal to simply come in contact with an ion reservoir 510, as described in PCT Patent Application No. PCT/US04/13836, filed May 3, 2004, already incorporated herein by reference, such barriers may be lacking in uniformity, which may be important in some embodiments. Accordingly, in a preferred embodiment of the invention the tunnel barrier does not significantly react with the ion reservoir 510 during fabrication.

With standard designs, the electric field at the tunnel barrier 505 is typically high enough to promote tunneling at thicknesses between 10 and 50 angstroms. The electric field is typically higher than at other points in the memory element 500 because of the relatively high serial electronic resistance of the electrolytic tunnel barrier 505. The high electric field of the electrolytic tunnel barrier 505 also penetrates into the ion reservoir 510 at least one Debye length. The Debye length can be defined as the distance which a local electric field affects distribution of free charge carriers. At an appropriate polarity, the electric field within the ion reservoir 510 causes ions (which can be positively or negatively charged) to move from the ion reservoir 510 through the electrolytic tunnel barrier 505, which is an ionic electrolyte.

The ion reservoir 510 is a material that is conductive enough to allow current to flow and has mobile ions. The ion reservoir 510 can be, for example, an oxygen reservoir with mobile oxygen ions. Oxygen ions are negative in charge, and will flow in the direction opposite of current.

FIG. 6A is a block diagram where a redox reaction between the oxygen reservoir 635 and a complementary reservoir 615 results in a low conductivity oxide 640 and an oxygen-depleted low conductivity region 620. In the case where the ion reservoir 510 is made up of negative oxygen ions, an appropriate complementary reservoir 615 would be positively charged ions. Additionally, the complementary reservoir 615 for the embodiment depicted in FIG. 6A should be conductive in its non-oxidized state and exhibit low conductivity in its oxidized state. Accordingly, many conductive metals (including alkali metals, alkaline earth metals, transition metals and other metals) could act as a complementary reservoir 615. For ease of fabrication, the complimentary reservoir 615 may be the non-oxidized form of the same material that is used for the electrolytic tunnel barrier 505.

When an electric field is applied across the electrolytic tunnel barrier 505, the electric field would penetrate at least one Debye length into the oxygen reservoir 635. The negatively charged oxygen ions migrate through the electrolytic tunnel barrier 505 to combine with positively charged metal ions in the complementary reservoir 615, creating a low conductivity oxide 640. This low conductivity oxide 640 is cumulative with the electrolytic tunnel barrier 505, forcing electrons to tunnel a greater distance to reach the conductive complimentary reservoir 615. Because of the exponential effect of barrier width on tunneling, the low conductivity oxide 640 can be just a few angstroms wide and still have a very noticeable effect on the memory element's effective resistance.

Those skilled in the art will appreciate that redox reaction can occur at either the top or bottom surface of the electrolytic tunnel barrier 505. The low conductivity oxide 640 will form at the top of the electrolytic tunnel barrier 505 if the mobility of the complementary ions is greater than the mobility of the oxygen ions through the electrolytic tunnel barrier 505. Conversely, if the mobility of oxygen ions is greater than the mobility of the complementary ions through the electrolytic tunnel barrier 505, then the low conductivity oxide 640 will form at the bottom of the electrolytic tunnel barrier 505.

The stability of metal oxides will depend on its activation energy. Reversing the redox reaction for many metal oxides, such as Hf and Al, requires a great amount of energy, making such high activation energy cells convenient for use as one-time programmable memories. Oxides with low activation energy, such as RuO_(X) and CuO_(X), are usually desirable for reprogrammable memories.

One optimization would be to use the polarity that is less sensitive to read disturbs during reads. For write once memory this may be complementary to the write polarity. Alternatively, alternating read polarities can be used. Another optimization for certain embodiments could be to limit the size of the complementary reservoir 615.

FIG. 6B is a block diagram where the complimentary reservoir 615 is fabricated to be self-limiting. Since only a small amount of the complementary reservoir 615 is deposited, the amount of positive ions available to combine with the free oxygen ions is limited. Once all the free ions in the complimentary reservoir 615 are consumed, no more low conductivity oxide 640 could be formed.

In most cases the effective width of the tunneling barrier is limited only by the availability of ions in the reservoirs 615 and 635. Since many different barrier widths can be formed multiple bits per cell can be easily implemented with different resistive states.

Referring back to FIG. 5A, certain ion reservoirs 510 have the physical property of being less conductive in an oxygen-deficient state. Some examples of materials that have mobile oxygen ions and are less conductive in an oxygen-deficient state include certain perovskites (a perovskite generally being in the form of an ABX₃ structure, where A has an atomic size of 1.0-1.4 Å and B has an atomic size of 0.45-0.75 Å for the case where X is either oxygen or fluorine) such as SrRuO₃ (SRO), Pr_(0.7)Ca_(0.3)MnO₃, Pr_(0.5)Ca_(0.5)MnO₃ and other PCMOs. Many of these ion reservoirs 510 are potentially mixed valence oxides. For example, PCMO might be more conductive when its manganese ion is in its Mn³⁺ state, but less conductive when its manganese ion is in its Mn⁴⁺ state.

Accordingly, as shown in FIG. 6A, certain oxygen reservoirs 635 will additionally form an oxygen-depleted low conductivity region 620 that also adds to the memory effect. Those skilled in the art will appreciate that either the oxygen-depleted low conductivity region 620 or the low conductivity oxide 640 may independently be sufficient to create an acceptable memory effect or, if the conduction mechanisms are different (e.g., small polaron hopping through the oxygen-depleted low conductivity region 620 and tunneling through the low conductivity oxide 640) one mechanism may even dominate the overall conduction through the memory element 500. Accordingly, memory cells can be designed to take advantage of only one phenomenon or the other or both.

Creating the Memory Effect with Oxygen Depletion

FIG. 7 is a block diagram representing another embodiment of a memory element 700 in a two-terminal memory cell where an oxygen-depleted low conductivity region in an otherwise conductive material creates the majority of the memory effect. FIG. 7 shows a mixed valence oxide 710 and a mixed electronic ionic conductor 705, two basic components of the memory element 700 between a top memory electrode 515 and a bottom memory electrode 520. As with the embodiment of FIG. 5A, the orientation of the memory element may be important for processing considerations. It should be appreciated that the memory element can also be used in a three-terminal memory cell, similar to what is depicted in FIG. 5C.

In these embodiments, ion deficiency (which, in the embodiment of FIG. 7, is oxygen) will cause an otherwise conductive material to become less conductive. The mixed valence oxide 710 will generally be crystalline, either as a single crystalline structure or a polycrystalline structure. In one specific embodiment the crystalline structure maintains its basic crystallinity (with some degree of deformation) in both valence states. By maintaining its crystallinity, both the physical stresses on the memory element may be reduced and the reversibility of the process may be easier to achieve.

The mixed electronic ionic conductor 705 is similar, and in some cases identical, to the electrolytic tunnel barrier 505 of FIGS. 6A and 6B. Like the electrolytic tunnel barrier 505, the mixed electronic ionic conductor 705 is both an electrolyte and creates a high electric field that promotes ionic movement. However, whether the mixed electronic ionic conductor 705 promotes actual tunneling is not critical.

In FIG. 8A the mixed electronic ionic conductor 705 also acts as an oxygen repository, temporarily holding oxygen until an opposite polarity voltage pulse pushes the oxygen back into the mixed valence oxide 710. In FIG. 8B a separate oxygen repository 715 layer is used to hold the oxygen. The oxygen repository 715 may be identical to the previously described complementary reservoir 615 or even certain types of oxygen reservoirs 635 such as IrO_(X). If a redox reaction creates an oxide in the oxygen repository 715, the activation energy required to disassociate the oxygen from the oxide will influence whether the memory is used as a one time programmable memory or a rewritable memory.

In one specific embodiment that is similar to an inverted embodiment of what is shown in FIG. 8A, the bottom electrode 520 might be a 500 Angstrom layer of platinum, DC magnetron sputtered with 180 watts applied to a platinum target in 4 mTorr of argon at 450° C. and then cooled in-situ for at least 10 minutes in the sputter ambient gas environment of 4 mTorr of argon.

The mixed valence oxide 710 might be a 500 Angstrom layer of a PCMO perovskite, RF magnetron sputtered in 10 mTorr of argon at 550° C. by applying 120 watts to a Pr_(0.7)Ca_(0.3)MnO₃ target (made with hot isostatic pressing or HIP), afterwards cooled in-situ for 10 minutes in the sputter ambient gas environment of 10 mTorr of argon, then cooled for another 10 minutes in a load lock chamber at 600 Torr of oxygen.

The mixed electronic ionic conductor 705 might be 20 or 30 Angstroms of some type of AlO_(X), RF magnetron sputtered in 4 mTorr of argon with 1% oxygen at 300° C. by applying 150 watts to an Al₂O₃ target (also made with HIP), and then annealed for 30 minutes at 250° C. in the sputter ambient gas environment of 4 mTorr of argon with 1% O₂.

If an embodiment similar to FIG. 8B were desired, an oxygen repository 715 of 200 Angstroms of aluminum metal could be DC magnetron sputtered with 250 watts applied to an aluminum target in 4 mTorr of argon at 25° C.

The top electrode 515 might be 500 Angstroms of platinum, DC magnetron sputtered with 180 watts applied to a platinum target in 4 mTorr of argon at 25° C.

Concluding Remarks

Although the invention has been described in its presently contemplated best mode, it is clear that it is susceptible to numerous modifications, modes of operation and embodiments, all within the ability and skill of those familiar with the art and without exercise of further inventive activity. For example, although the ion reservoir was described as being negative in connection with the oxygen reservoir, a positively charged ion reservoir may have the same functionality, as long as the other physical requirements of the specific embodiments are met. Furthermore, while the theories provided above are one possible explanation of how the various materials interact, the inventors do not wish to be bound by any theoretical explanation. Accordingly, that which is intended to be protected by Letters Patent is set forth in the claims and includes all variations and modifications that fall within the spirit and scope of the claims. 

The invention claimed is:
 1. A two-terminal memory cell comprising: a mixed valence oxide; a mixed electronic ionic conductor coupled with the mixed valence oxide; a first memory electrode in contact with the mixed valence oxide; and a second memory electrode coupled with the mixed electronic ionic conductor.
 2. The two-terminal memory cell of claim 1, wherein: the mixed electronic ionic conductor is uniform in conduction.
 3. The two-terminal memory cell of claim 1, wherein: the mixed electronic ionic conductor is lacking in uniformity in conduction.
 4. The two-terminal memory cell of claim 3, wherein: the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to the second memory electrode.
 5. The two-terminal memory cell of claim 3, wherein: the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to the second memory electrode.
 6. The two-terminal memory cell of claim 1, wherein: the mixed valence oxide is uniform in oxidation.
 7. The two-terminal memory cell of claim 1, wherein: the mixed valence oxide is lacking in uniformity in oxidation.
 8. The two-terminal memory cell of claim 7, wherein: the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the first memory electrode.
 9. The two-terminal memory cell of claim 8, wherein: the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the first memory electrode.
 10. The two-terminal memory cell of claim 1, wherein the mixed valence oxide is crystalline.
 11. A three-terminal memory cell comprising: a memory element comprising: a mixed valence oxide, and a mixed electronic ionic conductor coupled with the mixed valence oxide; a gate memory electrode coupled with the mixed valence oxide; a source memory electrode coupled with the memory element; and a drain memory electrode coupled with the memory element.
 12. The three-terminal memory cell of claim 11, wherein: the mixed electronic ionic conductor is uniform in conduction.
 13. The three-terminal memory cell of claim 11, wherein: the mixed electronic ionic conductor is lacking in uniformity in conduction.
 14. The three-terminal memory cell of claim 13, wherein: the uniformity of the mixed electronic ionic conductor varies in a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.
 15. The three-terminal memory cell of claim 13, wherein: the uniformity of the mixed electronic ionic conductor varies in a direction orthogonal to a direction from the mixed valence oxide to at least one of the source memory electrode and the drain memory electrode.
 16. The three-terminal memory cell of claim 11, wherein: the mixed valence oxide is uniform in oxidation.
 17. The three-terminal memory cell of claim 11, wherein: the mixed valence oxide is lacking in uniformity in oxidation.
 18. The three-terminal memory cell of claim 17, wherein: the uniformity of the mixed valence oxide varies in a direction from the mixed electronic ionic conductor to the gate memory electrode.
 19. The three-terminal memory cell of claim 17, wherein: the uniformity of the mixed valence oxide varies in a direction orthogonal to a direction from the mixed electronic ionic conductor to the gate memory electrode.
 20. The three-terminal memory cell of claim 11, wherein the mixed valence oxide is crystalline. 